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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . u l t r a - l o w o n - r e s i s t a n c e , 6 a d u a l l o a d s w i t c h w i t h s o f t s t a r t 16m w (typical) on-resistance per channel 6a continuous current s o f t s t a r t t i m e p r o g r a m m a b l e b y e x t e r n a l c a p a c i t o r wide input voltage range (vin): 0.8v to 5.5v supply voltage range (vbias): 3v to 5.5v output discharge when switch disabled reverse current blocking when switch disabled over-temperature protection the APL3533 is an ultra-low on-resistance, dual power- distribution switch with external soft start control. it inte- grates two n-channel mosfets that can deliver 6a con- tinuous load current each. the device integrates over-temperature protection. the over temperature protection function shuts down the n- channel mosfet power switch when the junction tem- perature rises beyond 160 o c and will automatically turns on the power switch when the temperature drops by 40 o c. the device is available in lead free tdfn2x3-14a packages. f e a t u r e s g e n e r a l d e s c r i p t i o n a p p l i c a t i o n s notebook aio pc s i m p l i f i e d a p p l i c a t i o n c i r c u i t enable input lead free and green devices available (rohs compliant) p i n c o n f i g u r a t i o n s en 1 3 14 vout 1 vin 1 1 vin 1 2 bias 4 13 vout 1 11 gnd 12 ss 1 tdfn 2 x 3 - 14 a ( top view ) vin 2 7 en 2 5 vin 2 6 10 ss 2 8 vout 2 9 vout 2 vin 1 vout 1 apl 3533 ss 2 en 1 v in 1 vout 2 vin 2 ss 1 en 2 bias v bias gnd on off v in 2 v out 1 v out 2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v bias bais to gnd voltage - 0.3 ~ 6 v v in1 , v in2 vi n 1, vin2 to gnd voltage - 0.3 ~ 6 v v out1 , v out2 vout1, vout2 to gnd voltage - 0.3 ~ 6 v v en1 , v en2 en1, en2 to gnd voltage - 0.3 ~ 6 v t j maximum junction temperature - 40 ~ 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature ( 10 seconds ) 26 0 o c note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja junction - to - ambient resistance in free air (note 2) 80 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. apl 3533 package code operating ambient temperature range i : - 40 to 85 o c handling code tr : tape & reel assembly material handling code temperature range package code g : halogen and lead free device assembly material qb : tdfn 2 x 3 - 14 a xxxxx - date code apl 3533 qb : l 3533 xxxxx
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 3 symbol parameter range unit v bias bias input voltage 3.0 ~ 5.5 v v in1 , v in2 vin1, vin2 input voltage 0.8 ~ 5.5 v i out vout1 or vout2 output current (single channel) 0 ~ 6 a p d maximum power dissipation, t a =50 o c (note4) 0.94 w v ih en1, en2 logic high in put voltage 1.2 ~ 5.5 v v il en1, en2 logic low input voltage 0 ~ 0.4 v t a ambient temperature - 40 ~ 85 o c t j junction temperature - 40 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) note 3 : refer to the typical application circuit. e l e c t r i c a l c h a r a c t e r i s t i c s unless otherwise specified, these specifications apply over v in1 = v in2 = 0.8v~5.5v, v en1 = v en2 =v bias =5v and t a = -40~85 o c. typical values are at t a =25 o c. apl3 533 symbol parameter test conditions min . typ . max . unit supply current bias supply current (both channels) no load, v bias =5v =v en1,2 =5v - 60 90 m a i bias bias supply current (single channel) no load, v bias =5v, v en1 =5v, v en2 =0v - 50 - m a i sd b ias supply current at shutdown no load, v bias =5v, v en1,2 =0v - - 2 m a no load, v bias =5v, v en1,2 =0v, v in1,2 =5v - 0.1 8 m a no load, v bias =5v, v en1 , 2 =0v, v in1,2 =3.3v - 0.1 3 m a no load, v bias =5v, v en1,2 =0v , v in1 , 2 =1.8v - 0.1 2 m a i off vin off - state supply current (per channel) no load, v bias =5v, v en1 , 2 =0v, v in1 , 2 =0.8v - 0.1 1 m a reverse leakage current (per channel) v en1 , 2 =0v, v in1 , 2 =0v - 0.1 16 m a under - voltage lockout (uvlo) rising bias uvlo threshold v bias rising 1.9 2.4 2.9 v bias uvlo hyst eresis - 0.1 - v power switch i out =200ma, t j = 2 5 o c - 16 18 m w i out =200ma, t j = - 40~ 12 5 o c channel 1 - - 24 m w i out =200ma, t j = 2 5 o c - 16 18 m w r ds(on) power switch on resistance i out =200ma, t j = - 40~ 12 5 o c channel 2 - - 24 m w vout discharge resi stance v en1,2 =0v, vout1 or vout2 force 1v - 150 180 w note 4 : refer to the thermal consideration on page 15.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s apl3 533 symbol parameter test conditions min . typ . max . unit soft - start control pin ss discharge current v ss1,2 =6v, v en1 , 2 =0v , en2=low, measured at ss1 or ss2 - 560 - m a en input pin input logic high 1.2 - - v input logic low - - 0.4 v in put current - - 1 m a overt - temperature protection (otp) over - temperature threshold t j rising - 160 - c over - temperature hysteresis - 40 - c unless otherwise specified, these specifications apply over v in1 = v in2 = 0.8v~5.5v, v en1 = v en2 =v bias =5v and t a = -40~85 o c. typical values are at t a =25 o c. t i m i n g c h a r t figure 1. t on /t off , t r /t f waveforms 90 % 90 % t r 10 % 10 % t f v out 50 % 50 % 50 % 50 % t off t d t on v out v en
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 5 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s quiescent current vs . bias supply voltage ( both channels ) q u i e s c e n t c u r r e n t , i b i a s ( m a ) 3 3 . 5 4 4 . 5 5 5 . 5 v bias = v in bias supply voltage , v bias ( v ) - 40 25 85 125 40 50 60 70 80 90 100 quiescent current vs . bias supply voltage ( single channel ) bias supply voltage , v bias ( v ) q u i e s c e n t c u r r e n t , i b i a s ( m a ) 3 3 . 5 4 4 . 5 5 5 . 5 v bias = v in 30 35 40 45 50 55 60 - 40 25 85 125 shutdown current vs . bias supply voltage ( both channels ) q u i e s c e n t c u r r e n t , i s d ( m a ) 3 3 . 5 4 4 . 5 5 5 . 5 bias supply voltage , v bias ( v ) v bias = v in 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 - 40 25 85 125 off - stage supply current vs . vin supply voltage ( single channel ) vin supply voltage , v in ( v ) o f f - s t a g e s u p p l y c u r r e n t , i o f f ( m a ) 3 3 . 5 4 4 . 5 5 5 . 5 v bias = 5 . 5 v - 40 25 85 125 0 2 4 6 8 10 12 14 - 40 0 25 50 75 100 125 switch on resistance vs . vin supply voltage vin supply voltage , v in ( v ) 0 . 5 1 1 . 5 2 2 . 5 3 12 14 16 18 20 22 24 26 28 30 32 v bias = 3 v s w i t c h o n r e s i s t a n c e , r d s ( o n ) ( m w ) - 40 0 25 50 75 100 125 switch on resistance vs . vin supply voltage vin supply voltage , v in ( v ) s w i t c h o n r e s i s t a n c e , r d s ( o n ) ( m w ) 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 12 13 14 15 16 17 18 19 20 21 22 23 24 v bias = 5 . 5 v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 6 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s v bias = 3 . 3 v v bias = 5 v switch on resistance vs . vin supply voltage t j = 25 c 14 15 16 17 18 19 20 21 22 23 24 0 . 5 1 . 5 2 . 5 3 . 5 4 . 5 5 . 5 vin supply voltage , v in ( v ) s w i t c h o n r e s i s t a n c e , r d s ( o n ) ( m w ) output current , i out ( a ) switch on resistance vs . output current 0 1 2 3 4 5 6 s w i t c h o n r e s i s t a n c e , r d s ( o n ) ( m w ) 14 15 16 17 18 v bias = 5 v , v in = 5 v , t j = 25 c 19 20 turn on delay time vs . vin supply voltage vin supply voltage , v in ( v ) t u r n o n d e l a y t i m e , t d ( m s ) 50 100 150 200 250 300 350 400 450 500 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 2 . 2 2 . 4 2 . 6 2 . 8 3 . 0 - 40 25 85 125 v bias = 3 v , r l = 10 w c ss = 1 nf , c out = 0 . 1 m f vin supply voltage , v in ( v ) t u r n o n d e l a y t i m e , t d ( m s ) 0 . 5 1 . 5 2 . 5 3 . 5 4 . 5 5 . 5 50 100 150 200 250 300 350 400 450 500 v bias = 5 . 5 v , c ss = 1 nf , r out = 10 w , c out = 0 . 1 m f turn on delay time vs . vin supply voltage - 40 25 85 125 falling time vs . vin supply voltage vin supply voltage , v in ( v ) f a l l i n g t i m e , t f ( m s ) 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 2 . 2 2 . 4 2 . 6 2 . 8 3 . 0 0 1 2 3 4 5 v bias = 3 v , r l = 10 w c ss = 1 nf , c out = 0 . 1 m f - 40 25 85 125 vin supply voltage , v in ( v ) f a l l i n g t i m e , t f ( m s ) 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 1 2 3 4 5 falling time vs . vin supply voltage v bias = 5 . 5 v , css = 1 nf , r out = 10 w , c out = 0 . 1 m f - 40 25 85 125
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 7 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s turn off time vs . vin supply voltage vin supply voltage , v in ( v ) t u r n o f f t i m e , t o f f ( m s ) 0 1 2 3 4 5 v bias = 3 v , r l = 10 w c ss = 1 nf , c out = 0 . 1 m f - 40 25 85 125 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 2 . 2 2 . 4 2 . 6 2 . 8 3 . 0 turn off time vs . vin supply voltage vin supply voltage , v in ( v ) t u r n o f f t i m e , t o f f ( m s ) 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 2 . 2 2 . 4 2 . 6 2 . 8 3 . 0 0 1 2 3 4 5 v bias = 5 . 5 v , r l = 10 w c ss = 1 nf , c out = 0 . 1 m f - 40 25 85 125 rising time vs . vin supply voltage vin supply voltage , v in ( v ) r i s i n g t i m e , t r ( m s ) 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 v bias = 3 v , r l = 10 w c ss = 1 nf , c out = 0 . 1 m f 0 200 400 600 800 1000 1200 1400 - 40 25 85 125 rising time vs . vin supply voltage vin supply voltage , v in ( v ) r i s i n g t i m e , t r ( m s ) v bias = 5 . 5 v , r l = 10 w c ss = 1 nf , c out = 0 . 1 m f 0 500 1000 1500 2000 2500 3000 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 - 40 25 85 125 turn on time vs . vin supply voltage vin supply voltage , v in ( v ) t u r n o n t i m e , t o n ( m s ) 0 200 400 600 800 1000 1200 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 v bias = 3 v , r l = 10 w c ss = 1 nf , c out = 0 . 1 m f - 40 25 85 125 turn on time vs . vin supply voltage vin supply voltage , v in ( v ) t u r n o n t i m e , t o n ( m s ) v bias = 5 . 5 v , r l = 10 w c ss = 1 nf , c out = 0 . 1 m f 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 0 200 400 600 800 1000 1200 1400 1600 1800 2000 - 40 25 85 125
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 8 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s rising time vs . bias supply voltage bias supply voltage , v bias ( v ) r i s i n g t i m e , t r ( m s ) 200 400 600 800 1000 1200 1400 1600 3 3 . 5 4 4 . 5 5 5 . 5 - 40 25 85 125 v in = 3 v , r l = 10 w c ss = 1 nf , c out = 0 . 1 m f
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 9 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . shutdown 1 3 2 ch 1 : v en , 2 v / div , dc ch 2 : v out , 200 mv / div , dc ch 3 : i out , 50 ma / div , dc time : 1 m s / div v bias = 3 v , v in = 0 . 8 v c out = 0 . 1 m f , c ss = 1 nf , r l = 10 w v en v out i out enable 1 3 2 ch 1 : v en , 2 v / div , dc ch 2 : v out , 200 mv / div , dc ch 3 : i out , 50 ma / div , dc time : 200 m s / div v bias = 3 v , v in = 0 . 8 v c out = 0 . 1 m f , c ss = 1 nf , r l = 10 w v en v out i out shutdown v en v out i out 1 3 2 ch 1 : v en , 2 v / div , dc ch 2 : v out , 200 mv / div , dc ch 3 : i out , 50 ma / div , dc time : 1 m s / div v bias = 3 v , v in = 0 . 8 v c out = 0 . 1 m f , c ss = 1 nf , r l = 10 w enable 1 3 2 v en v out i out ch 1 : v en , 2 v / div , dc ch 2 : v out , 200 mv / div , dc ch 3 : i out , 50 ma / div , dc time : 200 m s / div v bias = 3 v , v in = 0 . 8 v c out = 0 . 1 m f , c ss = 1 nf , r l = 10 w
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 0 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . shutdown ch 1 : v en , 2 v / div , dc ch 2 : v out , 1 v / div , dc ch 3 : i out , 200 ma / div , dc 1 3 2 v en v out iout v bias = 5 v , v in = 5 v c out = 0 . 1 m f , c ss = 1 nf , r l = 10 w enable 1 3 v en i out v out ch 1 : v en , 2 v / div , dc ch 2 : v out , 1 v / div , dc ch 3 : i out , 200 ma / div , dc time : 500 m s / div v bias = 5 v , v in = 5 v 2 c out = 0 . 1 m f , c ss = 1 nf , r l = 10 w
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 1 p i n d e s c r i p t i o n pin no. name function 1 vin1 2 vin1 power supply input of switch 1 . c onnect this pin to an external dc supply. 3 en1 enable input of switch 1. logic high turns on switch 1. the en1 pin cannot be left floating . 4 bias bias voltage input pin for inter nal control circuitry. 5 en2 enable input of switch 2. logic high turns on switch 2. the en2 pin cannot be left floating . 6 vin2 7 vin2 power supply input of switch 2 . c onnect this pin to an external dc supply. 8 vout2 9 vout2 switch 2 output. 10 s s2 soft start control of switch 2. a capacitor from this pin to ground sets the vout2 ? s rise slew rate. 11 gnd ground pin of the circuitry. all voltage levels are measured with respect to this pin. 12 ss1 soft start control of switch 1. a capacitor from this pin to ground sets the vout1 ? s rise slew rate. 13 vout1 14 vout1 switch 1 output.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 2 b l o c k d i a g r a m uvlo vin 1 vout 1 charge pump en 1 gnd ss 1 bias bulk select control logic otp 1 bulk select en 2 vin 2 vout 2 ss 2 charge pump otp 2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 3 t y p i c a l a p p l i c a t i o n c i r c u i t soft - start time ( m s) 10% to 90%, v bias =5v, c l =0.1 m f, c in =1 m f, r l =10 w , typical values are at t a =25c c ss (pf) v in =5v v in =3.3v v in =1.8v v in =1.5v v in =1.2v v in =1.05v v in =0.8v 0 112 73 53 49 45 42 38 220 492 322 197 170 146 132 128 330 685 450 270 230 198 1 80 145 470 911 598 355 307 263 233 188 1000 2030 1280 749 635 538 470 388 2200 4360 2740 1574 1336 1118 1014 797 4700 8780 5540 3218 2696 2289 2037 1624 10000 19060 12011 6862 5700 4806 4301 3410 note: the table contains soft-start time values measured on a typical device. the soft-start times shown are only valid for the power- up sequence where v in and v bias are already in steady state condition, and en pin is asserted high. vin 1 vout 1 apl 3533 ss 2 en 1 vout 2 vin 2 ss 1 en 2 bias gnd c ss 2 8 , 9 13 , 14 10 11 12 c ss 1 r load 1 c l 1 150 m f c out 1 0 . 1 m f 150 v in 1 c in 1 1 m f v bias on off c bias 0 . 1 m f v in 2 1 , 2 6 , 7 3 5 4 c in 2 1 m f 0 . 1 m f c out 2 c l 2 m f r load 2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 4 f u n c t i o n d e s c r i p t i o n vin under-voltage lockout (uvlo) a under-voltage lockout (uvlo) circuit monitors the vbias pins voltage to prevent wrong logic controls. the uvlo function initiates a soft-start process after the bias sup- ply voltages exceed rising uvlo voltage threshold dur- ing powering on. power switch the power switch is an n-channel mosfet with a ultra- low r ds(on) . when ic is in shutdown state (v en1,2 =0v), the mosfet prevents a reverse current flowing from the vout back to vin. when ic is in uvlo state, the internal para- sitic diodes connected from vout to vin will be forward biased. soft-start the APL3533 provides an adjustable soft-start circuitry to control rise rate of the output voltage and limit the cur- rent surge during start-up. the soft-start time is set with a capacitor from the ss pin to the ground. enable control the APL3533 has a dedicated enable pin (en). a logic low signal applied to this pin shuts down the output. fol- lowing a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle. over-temperature protection (otp) when the junction temperature exceeds 160 o c, the inter- nal thermal sense circuit turns off the power fet and allows the device to cool down. when the device?s junc- tion temperature cools by 40 o c, the internal thermal sense circuit will enable the device, resulting in a pulsed output during continuous thermal protection. thermal protection is designed to protect the ic in the event of over temperature conditions. for normal operation, the junction temperature cannot exceed t j =+125 o c.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 5 a p p l i c a t i o n i n f o r m a t i o n power sequencing capacitor selection the APL3533 requires proper input capacitors to supply current surge during stepping load transients to prevent the input voltage rail from dropping. because the para- sitic inductor from the voltage sources or other bulk ca- pacitors to the vin pin limit the slew rate of the surge currents, more parasitic inductance needs more input capacitance. for normal applications (except otp or output short cir- cuit has occurred), the recommended input capacitance of vin is 1 m f and output capacitance of vout is 0.1 m f at least. please place the capacitors near the APL3533 as close as possible. a bulk output capacitor, placed close to the load, is rec- ommended to support load transient current. soft-start capacitor the soft-start capacitor on ss pin can reduce the inrush current and overshoot of output voltage. the capacitor is charge to v ss with a constant current source. this results in a linear charge of the soft-start capacitor and thus the output voltage. the APL3533 has a built-in reverse current blocking cir- cuit to prevent a reverse current flowing through the body diode of power switch from the vout back vin pin when power switch disabled. the reverse current blocking cir- cuit is not active before v bias is ready. when ic is in uvlo state, the internal parasitic diodes of power switch con- nected from vout to vin will be forward biased. otherwise, vout should not be higher than vbias, and vbias must be higher than the voltage of any other input pin, the reason is that the internal parasitic diodes con- nected from vout to vbias will be forward biased. figure 2. APL3533 power sequencing diagram t h e r m a l c o n s i d e r a t i o n t h e a p l 3 5 3 3 m a x i m u m p o w e r d i s s i p a t i o n d e p e n d s o n t h e d i f f e r e n c e s o f t h e t h e r m a l r e s i s t a n c e a n d t e m p e r a - t u r e b e t w e e n j u n c t i o n a n d a m b i e n t a i r . t h e p o w e r d i s s i - p a t i o n p d a c r o s s t h e d e v i c e i s : p d = ( t j - t a ) / q j a w h e r e ( t j - t a ) i s t h e t e m p e r a t u r e d i f f e r e n c e b e t w e e n t h e j u n c t i o n a n d a m b i e n t a i r . q j a i s t h e t h e r m a l r e s i s t a n c e b e t w e e n j u n c t i o n a n d a m b i e n t a i r . a s s u m i n g t h e t a = 2 5 c a n d m a x i m u m t j = 1 6 0 c ( t y p i c a l t h e r m a l l i m i t t h r e s h o l d ) , t h e m a x i m u m p o w e r d i s s i p a t i o n i s c a l c u l a t e d a s : p d ( m a x ) = ( 1 6 0 - 2 5 ) / 8 0 = 1 . 6 8 ( w ) f o r n o r m a l o p e r a t i o n , d o n o t e x c e e d t h e m a x i m u m o p e r - a t i n g j u n c t i o n t e m p e r a t u r e o f t j = 1 2 5 c . t h e c a l c u l a t e d p o w e r d i s s i p a t i o n s h o u l d b e l e s s t h a n : p d = ( 1 2 5 - 2 5 ) / 8 0 = 1 . 2 5 ( w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t a = 2 5 o c p d = ( 1 2 5 - 8 5 ) / 8 0 = 0 . 5 ( w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t a = 8 5 o c the power dissipation depends on operating ambient temperature for fixed t j =125 o c and thermal resistance q ja . for APL3533 packages, the figure 3 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 1 . 2 1 . 3 - 40 - 30 - 20 - 10 0 10 20 30 40 50 60 70 80 90 ambient temperature ( o c ) p o w e r d i s s i p a t i o n ( w ) figure 3. d e r a t i n g c u r v e s f o r a p l 3 5 3 3 p a c k a g e v out 1 , v out 2 v en 1 , v en 2 v in 1 , v in 2 v en 1 , v en 2 v out 1 , v out 2 v in 1 , v in 2 v bias v bias
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 6 a p p l i c a t i o n i n f o r m a t i o n recommended minimum footprint layout consideration the pcb layout should be carefully performed to maxi- mize thermal dissipation and to minimize voltage drop, droop and emi. the following guidelines must be considered: 1. please place the input capacitors near the vin pin as close as possible. 2. output decoupling capacitors for load must be placed near the load as close as possible for decoupling high frequency ripples. 3. locate APL3533 and output capacitors near the load to reduce parasitic resistance and inductance for excellent load transient performance. 4. the negative pins of the input and output capacitors and the gnd pin must be connected to the ground plane of the load. 5. keep vin and vout traces as wide and short as possible. 0 . 25 ( 0 . 01 ) 0 . 48 ( 0 . 0192 ) 0 . 4 ( 0 . 016 ) tdfn 2 x 3 - 14 a unit : mm , ( inch ) 1 . 3 ( 0 . 051 )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 7 t d f n 2 x 3 - 1 4 a p a c k a g e i n f o r m a t i o n pin 1 d e a b a 1 a 3 nx aaa c seating plane d 2 e p i n 1 c o r n a r l s y m b o l min . max . 0 . 80 0 . 00 0 . 15 0 . 25 2 . 90 3 . 10 0 . 05 0 . 30 a a 1 b d e e l millimeters a 3 0 . 11 ref tdfn 2 x 3 - 14 a 0 . 40 0 . 004 ref min . max . inches 0 . 031 0 . 000 0 . 006 0 . 010 0 . 114 0 . 122 0 . 012 0 . 70 0 . 016 0 . 028 0 . 002 0 . 40 bsc 0 . 016 bsc 1 . 90 2 . 10 0 . 075 0 . 083 aaa 0 . 08 0 . 003
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 8 c a r r i e r t a p e & r e e l d i m e n s i o n s a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d application a h t1 c d d w e1 f 178.0 ? 2.00 50 min. 8.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 8.0 ? 0.20 1.75 ? 0.10 3.50 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn2x3 - 14a 4.0 ? 0.10 4.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.25 ? 0.05 2.3 0 ? 0.20 3.30 ? 0.20 1.00 ? 0.20 (mm) d e v i c e s p e r u n i t package type unit quantity tdfn2x3 - 14a tape & reel 3000
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 1 9 t a p i n g d i r e c t i o n i n f o r m a t i o n t d f n 2 x 3 - 1 4 a c l a s s i f i c a t i o n p r o f i l e user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 2 0 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ tj=125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - m a r . , 2 0 1 3 a p l 3 5 3 3 w w w . a n p e c . c o m . t w 2 1 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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